Understanding Unijunction Transistor Circuit Design and Symbols

For a reliable relaxation oscillator, place the programmable two-terminal device between a voltage divider and a timing capacitor. Connect the first base (B1) to ground through a 100 Ω resistor and the second base (B2) to a supply voltage via a 1 kΩ resistor. The emitter (E) should link directly to the capacitor–typically 0.1 µF–to ensure rapid charging and discharging cycles. Adjust the B2 resistor ratio to fine-tune the intrinsic stand-off ratio (η) between 0.5 and 0.8 for stable oscillation.

Trace the current path: when the emitter voltage reaches η × V_BB, the device triggers, dumping capacitor charge into B1. This creates a sharp voltage drop across the emitter resistor (often 50–200 Ω), pulling the emitter below the threshold and resetting the cycle. Avoid using electrolytic capacitors–film or ceramic types prevent phase drift. If oscillation ceases, verify the B2 resistor isn’t exceeding 5 kΩ, which can push the device into saturation and kill switching action.

For pulse generation, swap the timing capacitor with a lower value (10–100 nF) and add a 10 kΩ load resistor from B1 to ground. This sharpens rise times, reducing jitter in timing applications. Keep leads short–parasitic inductance above 100 nH distorts waveforms. Test with a dual-channel scope: probe emitter and B1 to confirm complementary voltage swings. If amplitude sags, check the supply ripple–clean 12 V DC outperforms unstable linear regulators.

Key Components in a Two-Terminal Negative Resistance Device Circuit

Start by placing the emitter (E) at the midpoint of a lightly doped bar with two ohmic contacts–base 1 (B1) and base 2 (B2)–forming a voltage divider. Apply a supply between B2 and B1, ensuring the emitter voltage V_E remains below V_P (peak point), typically 60-70% of V_BB, to keep the device in cutoff. For silicon structures like the 2N2646, η (intrinsic standoff ratio) ranges from 0.56 to 0.75; use this to calculate V_P = ηV_BB + 0.6V for precise triggering.

Connect a resistor R_E (100Ω to 1kΩ) between the emitter and ground to limit current during the negative resistance region, preventing thermal runaway. Add a timing capacitor C_E (0.01µF to 10µF) in parallel to R_E to define pulse width; discharge through the emitter-B1 path yields a rise time under 50ns for 2N2646 at V_BB = 12V. Ensure R_B1 (typically 50Ω to 200Ω) is small enough to avoid loading effects on the pulse amplitude, which should reach 80-90% of V_BB.

To stabilize temperature drift, add a compensation resistor R_B2 (1kΩ to 10kΩ) between B2 and the supply; match it to the device’s thermal coefficient (for 2N2646, ~0.8mV/°C). Use a bypass capacitor (0.1µF) across V_BB to suppress supply noise, critical for consistent V_P triggering in timing applications. Avoid exceeding V_BB = 35V for most small-signal variants; higher voltages risk exceeding the breakdown limit of ~60V and degrading the junction.

For oscillation circuits, set R_EC_E time constant to control frequency (f ≈ 1/(RC ln(1/(1−η)))); with η = 0.65 and C_E = 0.1µF, a 1kΩ resistor yields ~1.5kHz. Verify the valley point V_V (~2-3V) and valley current I_V (1-5mA) to ensure proper reset before the next cycle; insufficient I_V causes sporadic triggering. Use a scope probe (10x, ≤10pF capacitance) to measure emitter waveforms–excessive probe loading distorts the negative resistance region, skewing results.

In thyristor gate triggering, couple the B1 output via a 10µF capacitor to isolate DC; amplitude peaks above 8V reliably switch SCRs like the C106 without false triggering. For high-reliability designs, derate V_BB to 80% of max and operate within 50% of I_E(max) (e.g., 50mA for 2N2646) to extend lifespan beyond 10,000 hours. Replace the device if η drifts ±5%–earliest sign of junction degradation.

Key Components in a Basic Two-Terminal Negative Resistance Device Circuit

Select the emitter resistor (RE) between 5 kΩ and 50 kΩ to ensure stable operation without excessive current. Values below 3 kΩ risk latching, while above 100 kΩ reduce triggering sensitivity. Experiment with 10 kΩ for general-purpose applications.

The timing capacitor (C) directly controls oscillation frequency–10 nF yields ~1 kHz, while 1 µF drops to ~10 Hz. Leakage must be minimal; polyester or polypropylene types outperform ceramic for consistency. Avoid electrolytic capacitors if drift under 0.5% is required.

Base-two series resistor (RB2) should match the device’s interbase resistance (typically 5 kΩ–10 kΩ) to avoid altering intrinsic stand-off ratio. A 4.7 kΩ fixed resistor fits most silicon-based variants, but verify datasheet for ±20% tolerance adjustments.

Add a 1 kΩ–10 kΩ pull-down resistor (RG) between emitter and ground to prevent false triggers from noise. Omitting this can cause erratic firing in high-impedance environments. Bypass with a 0.1 µF ceramic capacitor if electromagnetic interference exceeds 50 mVpp.

Critical Device Parameters

Verify η (intrinsic stand-off ratio) before assembly–measuring 0.56–0.75 confirms manufacturability. Apply a precision multimeter across B2-B1 leads with VBB = 10 V; divide the result by 10 to derive η. Reject devices where η deviates >±0.05 from published specs.

Temperature stability hinges on RBB drift. For 2N2646 equivalents, expect 0.8%/°C rise–compensate with a parallel NTC thermistor (10 kΩ at 25°C) across B2. Mount within 5 mm of the device case for thermal coupling. Failure to compensate yields frequency shifts exceeding 15% across -20°C to +85°C.

Emitter current (IE) peak during valley point must exceed 1 mA to sustain negative resistance region. Reduce RE incrementally until IE stabilizes; below 500 µA, conduction collapses unpredictably.

Power dissipation limits (PD) demand heatsink for continuous operation above 10 mW. TO-92 packages tolerate 350 mW at 25°C; derate linearly to 0 mW at 150°C. Use a 2°C/W sink for surface-mount variants to prevent thermal runaway during prolonged relaxation oscillation.

How to Identify and Label UJT Leads in Circuit Drawings

Locate the emitter terminal first–the single lead offset from the other two on the component’s symbol. It typically forms a diagonal line extending from the central vertical axis, distinct from the base connections.

Distinguish the two base terminals by their positioning: B1 sits at the bottom of the vertical line, while B2 connects midway, often closer to the emitter. Manufacturers mark B1 as the primary reference point for biasing.

• Trace the curved arrow (emitter) backward to its intersection point–this confirms B2.
• Check datasheets for pin numbering; some variants reverse B1/B2 despite identical symbols.
• Avoid relying on proximity alone–verify via resistance checks: B1-B2 should measure ~5–10 kΩ, emitter-B1 ~1–5 kΩ when reverse-biased.

Confirm polarities by testing with a multimeter in diode mode. The emitter should show low forward voltage (~0.6–0.7 V) to B2 but higher (~1.0–1.5 V) to B1 due to internal doping gradients.

Label terminals directly on the drawing using standardized notation:

1. Use E for emitter.
2. Append B1 and B2 near their respective leads.
3. Indicate polarity with + or – symbols if the circuit requires fixed bias.

Cross-reference with physical packages. TO-92 variants position E on the left, B2 center, B1 right when viewing the flat face. Larger metal-can types (e.g., TO-18) mirror this but include a dot marking E.

Document variations in schematics for programmable devices (e.g., PUTs). These may label interchangeable bases as Anode/Gate/Cathode–add parenthetical notes like (B2/Gate) to prevent confusion during assembly.

Step-by-Step Guide to Drawing a Relaxation Oscillator with a Double-Base Device

Select a dynamic semiconductor with three leads: an emitter (E) and two bases (B1, B2). Verify its intrinsic standoff ratio (η) from the datasheet–typically between 0.5 and 0.8–since this determines the charging threshold.

Connect a timing capacitor (C) between the emitter and ground. For oscillation frequencies in the audio range (1 Hz to 10 kHz), use values from 0.01 µF to 1 µF. Lower capacitance yields higher frequency, but stray capacitance imposes a practical lower limit near 100 pF.

Attach a resistor (R) between the emitter and a positive supply voltage (V_BB). Calculate R using the formula R ≈ (V_BB × η) / (I_E × f), where I_E is the emitter current (usually 10–50 µA) and f is the target frequency. For V_BB = 12V, η = 0.65, and f = 1 kHz, R ≈ 156 kΩ.

Capacitor (C)	Resistor (R) Range	Frequency Range
0.01 µF	22 kΩ – 220 kΩ	500 Hz – 5 kHz
0.1 µF	10 kΩ – 1 MΩ	50 Hz – 500 Hz
1 µF	1 kΩ – 10 MΩ	5 Hz – 50 Hz

Link B2 directly to V_BB through a 100–470 Ω resistor to stabilize the valley point. Ground B1 or connect it via a small resistor (≤ 100 Ω) if triggering modifications are needed. Avoid leaving B1 floating, as this introduces instability.

Add a load resistor (R_L) of 50–500 Ω between B1 and ground for current output. The voltage spike across R_L during discharge will approximate a sawtooth waveform with a peak amplitude of V_BB × (1 – η). For η = 0.7, expect peaks near 3.6V when V_BB = 12V.

Test the circuit by monitoring the emitter voltage with an oscilloscope. Adjust R until the charging ramp matches the target frequency. If the waveform distorts, reduce R_L or increase C to lower impedance. For fine-tuning, replace R with a potentiometer in series with a fixed resistor (e.g., 10 kΩ + 1 MΩ pot).

Limit V_BB to the device’s maximum rating–often 30V–to prevent thermal runaway. Use a decoupling capacitor (0.1 µF) across V_BB and ground to filter noise, particularly in high-impedance circuits where stray coupling may alter η.