Complete Lisn Circuit Schematic Guide with Wiring and Components

For accurate conducted emissions testing, integrate a 50Ω/50μH line impedance stabilization network (LISN) between the equipment under test (EUT) and its power source. Position the network’s measurement port no closer than 80 cm from the EUT to prevent near-field coupling distortions. Ensure the ground plane beneath the network extends at least 2 meters beyond its boundaries–this minimizes resonance effects that skew readings below 30 MHz.

Select a dual-channel configuration when testing three-phase systems: isolate each phase with separate stabilization networks (SN) to avoid phase imbalance errors. Connect the neutral conductor to a dedicated SN, even if unpowered–floating neutrals introduce ±6 dB variations in results. Terminate unused network ports with 50Ω RF loads; unterminated ports act as unintended antennas, amplifying ambient noise by 15–22 dB.

Calibrate the SN’s path loss annually using a 10 kHz–100 MHz tracking generator and spectrum analyzer. Record attenuation curves at 1 MHz intervals–deviations exceeding ±1.5 dB indicate degraded inductors or corroded connectors. Replace 50μH air-core inductors if DC resistance exceeds 0.12Ω; higher values increase voltage drop, invalidating test limits under CISPR 25 Class 5.

For battery-powered EUTs, insert a 470μF capacitor across the SN’s EUT-side terminals to stabilize transient voltages. Omit this step during radiated emissions scans–capacitive loading alters impedance, producing false 2–3 dB peaks at harmonics of the switching frequency. Use ferrite beads on the measurement cable’s outer shield to suppress shield-current-induced noise, but verify they introduce <0.5 dB loss at 100 MHz to preserve measurement fidelity.

Log network schematics with component tolerances (e.g., ±5% for inductors) and real-world impedance plots from 150 kHz to 30 MHz. Document deviations between simulated and measured SN impedance–discrepancies above 15% require derating test limits by the same percentage. Store schematics in vector format (not raster) to allow scaling for future revisions without quality loss.

Understanding Line Impedance Stabilization Networks

Start with a 50 µH inductor on the power input side to filter high-frequency noise while maintaining a stable impedance. Pair it with a 1 µF capacitor connected to ground immediately after–this combination reduces conducted emissions by attenuating frequencies above 10 kHz. For accurate measurements, ensure the network’s impedance remains within 50 Ω ±5% across the 10 kHz to 100 MHz range to match standard test equipment specifications.

Use non-polarized film capacitors rated for at least 50V DC to avoid leakage current distortion. A parallel 1 kΩ resistor across the measurement output creates a controlled discharge path, preventing voltage build-up during testing. Avoid ceramic capacitors below 1 nF; their piezoelectric effects can introduce misleading harmonics in low-level signal analysis.

Ground the stabilizer’s reference plane directly to a solid metal chassis–no more than 20 mm from the test point–to eliminate ground loops. For multi-phase systems, replicate the same component values per line to maintain symmetry; even minor mismatches (e.g., 3% tolerance deviations) can skew harmonic readings by up to 2 dB.

Verify performance with a spectrum analyzer set to 1 Hz resolution bandwidth. Peak emissions should drop below -80 dBµV at 1 MHz when powered by a clean 12V DC source. If readings exceed -50 dBµV, inspect for loose connections or parasitic inductance in solder joints–common culprits in high-frequency noise coupling.

Key Elements and Their Graphical Representations in Line Impedance Stabilization Networks

Begin by identifying the resistor symbol–a rectangular box with labeled resistance–since it defines the primary impedance path in the stabilization setup. Common values range from 50 Ω to 1 kΩ, selected based on frequency requirements. For high-frequency accuracy, prioritize precision resistors with tight tolerances (±1% or better) to minimize signal reflections.

Inductors appear as coiled lines and serve dual purposes: blocking unwanted RF interference while allowing desired signals. Core material significantly impacts performance–ferrite cores excel in EMI suppression above 1 MHz, while air cores reduce parasitic capacitance in high-frequency designs. Pair inductors with capacitors (shown as parallel lines) to form a resonant filter, tuning the network’s cutoff frequency.

Capacitors in these schematics typically use ceramic or film types for stability across temperature variations. Values between 0.1 µF and 10 µF suit most applications, but verify self-resonant frequency to avoid counterproductive effects. Ground symbols–a downward-pointing triangle–must connect all components to a single reference plane to prevent ground loops, which distort measurements.

  • Coaxial connector: Depicted as a circle with a central dot, ensure center conductor impedance matches system requirements (e.g., 50 Ω). Mismatches introduce standing waves.
  • Transformer: Represented by coupled inductors, isolate measurement paths while maintaining signal integrity. Check winding ratios to confirm compatibility with expected voltage levels.
  • Ferrite bead: A small rectangle on the trace, used to dampen high-frequency noise without affecting DC performance. Select beads with impedance curves matching the target frequency range.

Voltage dividers–combinations of resistors–require precise calculation to avoid loading effects. Use the formula Vout = Vin × (R2 / (R1 + R2)) but account for stray capacitance, especially above 1 MHz. Verify component placement on the layout: keep high-impedance paths short to reduce pickup, and avoid routing sensitive traces near switching elements.

Step-by-Step Assembly of a RF Measurement Network on a Prototype Board

Select a compact prototype board with at least 800 tie points, ensuring the power rails run along both edges for symmetric component placement. Position the 50-ohm coaxial connector’s signal pin at the upper-left corner, leaving 3 rows of unused holes between the connector and the first passive element to minimize parasitic coupling.

Component Placement Order

Solder the 0.1 µF capacitor immediately adjacent to the connector’s ground lug to establish a low-impedance return path; orientation polarity is irrelevant. Mount the 1 µH inductor horizontally, rotating it 90° to the capacitor leads–keep leads shorter than 5 mm to avoid self-resonant effects above 30 MHz. Install the 1 kΩ resistor vertically, bridging the inductor’s output node to the board’s lower power rail; verify post-solder resistance with a multimeter set to 2 kΩ range.

Route the output tap point via a 22 AWG solid wire, stripping 2 mm of insulation and bending the exposed conductor into a tiny hook to fit into the inductor-resistor junction hole; secure the hook with a single dab of low-temperature solder to prevent melting adjacent joints. Install a ferrite bead directly on the power rail between the resistor and the main supply entry point–ensure the bead’s inner diameter is no larger than 1.5 mm to maintain >30 dB attenuation at 10 MHz.

Ground Plane Implementation

Cut a 0.1 mm copper foil strip to span the entire bottom border of the board, overlapping the existing ground rails by 2 mm. Secure the foil with conductive adhesive, then solder the foil’s left edge to the coaxial connector’s ground lug and its right edge to the power rail at three equidistant points, spacing each joint ≤20 mm apart–measure continuity after each solder joint with a milliohm meter to confirm

Power the configuration with a linear regulated supply delivering 5 VDC ±2 %, bypassed at the board entry by a 47 µF tantalum capacitor mounted upright less than 10 mm from the bead–position the capacitor’s negative terminal toward the rail to minimize ground loops. Verify assembled network impedance with a vector network analyzer in one-port reflection mode; expect |S11|

Determining Impedance for Precise EMI Network Analysis

Begin by identifying the target frequency range for conducted emissions testing. For CISPR 22 Class B compliance, the standard mandates an impedance of 50Ω ± 20% between 150 kHz and 30 MHz. Verify this with a calibrated network analyzer before each measurement cycle. Deviations exceeding 5Ω at key frequencies (1 MHz, 10 MHz, 30 MHz) necessitate capacitor or inductor adjustments in the coupling network.

Use a vector impedance meter to measure the exact phase angle between voltage and current at critical points. The EUT’s input impedance often introduces reactive components that skew results. A 10nF coupling capacitor with ±5% tolerance reduces phase errors below 3° at 1 MHz, while a 5μH common-mode choke maintains impedance stability within ±1.5Ω up to 10 MHz.

Account for parasitic elements by calculating their impact on the equivalent series resistance (ESR). A 1mΩ ESR shift in a 47μF capacitor can alter impedance readings by 8% at 500 kHz. Replace electrolytic components with film or ceramic types when ESR exceeds 0.5Ω. For high-current applications, parallelize inductors to distribute heat and prevent saturation, ensuring inductance drift stays below 2%.

Implement a 4-wire Kelvin connection for impedance measurements above 1 MHz to eliminate lead resistance errors. Probe placement accuracy is critical–maintain less than 2mm spacing between voltage and current leads on copper traces. Ground plane separation must exceed 20mm to prevent capacitive coupling, which can introduce a 15Ω error at 30 MHz in poorly designed setups.

Adopt a sweep frequency method instead of fixed-point measurements to detect abrupt impedance changes. A 50Ω reference standard should calibrate the analyzer at 100 kHz intervals. Software compensation (e.g., polynomial fitting) can correct minor deviations, but manual trimming of inductors or resistors remains necessary when errors exceed ±3Ω. Store baseline data in CSV format for trend analysis.

Validate the network’s impedance with a known 20dB attenuator as a dummy load before connecting the EUT. Any deviation from the expected 50Ω must be documented and corrected–typical sources include solder flux residue (increases ESR by 0.3Ω) or improper toroid winding alignment (alters inductance by 4%). Post-test, remeasure impedance at half-load and full-load conditions to confirm stability across varying current draw scenarios.