IR2104 MOSFET Driver Circuit Diagram and Practical Schematic Example

To build a robust gate driver layout, begin with a 24V isolated supply feeding the high-side floating channel. Place a 1μF bootstrap capacitor directly between the VB and VS pins, ensuring its leads are no longer than 5mm to minimize parasitic inductance. The diode–preferably a 1N4148 or schottky–must block the full rail voltage (up to 600V in high-voltage applications) and handle at least 1A peak current. Omit decoupling capacitors at your peril: a 0.1μF ceramic across VCC and COM stabilizes the logic supply, while a 10μF electrolytic absorbs transient dips during switching.

Connect the output stage with 10Ω gate resistors for standard TO-220 MOSFETs; reduce to 4.7Ω for faster edges in low-inductive loads like 20 kHz motor drives. Locate these resistors within 10mm of the gate pad to prevent ringing–excessive trace length couples noise into the driver’s internal latch, risking false triggering. Add a 1kΩ pull-down resistor at the input to enforce known logic states during power-up, especially in noisy environments like solar inverters.

Ground the COM pin to the source of the low-side MOSFET using a star topology–never share this node with high-current paths. For high-frequency layouts (>50 kHz), route the bootstrap diode’s cathode trace as a separate pour directly to the capacitor, avoiding any shared vias. Thermal reliefs on the VS node can improve solderability but increase impedance; balance manufacturability against performance by keeping vias diameter ≥0.5mm while minimizing their count.

Test the configuration with a 50% duty cycle, 20 kHz PWM signal from a microcontroller; monitor VS with a differential probe set to 1V/div. Proper operation shows VS toggling between 0V and +12V, while errors–such as overvoltage spikes or incomplete transitions–point to excessive load inductance or incorrect bootstrap replenishment. For 3-phase bridge applications, stagger the driver’s shutdown delays (adjustable via the SD pin pulldown) to prevent shoot-through faults, even with dead-time compensation enabled in firmware.

Building a High-Side/Low-Side Driver: Step-by-Step Integration

Start with a bootstrap capacitor rated for at least 10× the gate charge of your MOSFET. For 200V applications, a 1μF ceramic capacitor with X7R dielectric prevents voltage droop during switching. Place it between VB and VS pins, ensuring the trace length is under 5mm to minimize inductance. Add a 1N4007 diode in series with the bootstrap path for reverse-voltage protection during dead-time intervals.

Power the logic section (VCC pin) with a regulated 12V supply, decoupled with a 10μF tantalum capacitor and a 0.1μF ceramic capacitor mounted within 2mm of the pin. Ensure VSS (ground reference) is star-connected to the MOSFET source and load return path to prevent ground bounce exceeding 100mV. For proper gate drive, calculate the series resistor using R = V_driver / (2 × I_gate_max), where I_gate_max is the peak current specified in the MOSFET datasheet, typically 1–2A.

Implement dead-time between high-side and low-side transitions by selecting a pull-up resistor for LIN and a pull-down for HIN. A 10kΩ resistor on LIN creates ~500ns delay when driving from a 3.3V microcontroller; adjust resistance for longer delays if shoot-through current exceeds 1A. Add a 10Ω resistor in series with each gate to dampen oscillations, visible on an oscilloscope as sub-50ns ringing at turn-off.

Verify switching behavior by probing HO and LO outputs with differential probes set to 10× attenuation. The high-side output should swing between VB and VS potentials, with no more than 5% overshoot at 20MHz bandwidth. If ringing persists, increase the gate resistor to 22Ω or add a 1nF ceramic capacitor in parallel to the MOSFET gate-source terminals. For layout, route power loops (VB-VS and VCC-VSS) with 2oz copper traces, keeping loop area under 20mm² to reduce radiated EMI below 50dBμV.

Test load driving with a 10Ω power resistor and an inductive load rated for 3× your nominal current. Monitor VS pin voltage during turn-on; it should not drop below COM by more than 0.7V. If it does, increase bootstrap capacitor value to 2.2μF or reduce switching frequency below 100kHz. For fail-safe operation, add a 5.1V Zener diode across the gate-source terminals to clamp transients during load faults.

Pin Configuration and Signal Roles in Half-Bridge Driver ICs

Align the VS pin (pin 2) to the source of the low-side MOSFET to stabilize the reference voltage for gate drive outputs. A 10-100nF ceramic capacitor must bridge VS to COM (pin 1) within 2mm of the package to suppress high-frequency noise and ensure clean switching transitions. Omitting this or placing the capacitor farther than 5mm introduces transient voltage spikes exceeding 5V, risking false turn-on of the power devices.

Drive the high-side MOSFET via HO (pin 7) with a 10–20V supply referenced to VB (pin 8). VB itself requires a bootstrap capacitor–typically 0.1µF, X7R–connected directly between VB and VS. The capacitor’s ESR must stay below 100mΩ to maintain sufficient voltage during the 1µs dead-time interval. Exceeding 200mΩ causes voltage sag below 9V, triggering undervoltage lockout.

Input Signal Protocol

Feed logic-level PWM signals (3.3V or 5V) into HIN (pin 3) for high-side control and LIN (pin 5) for low-side control. Internal pull-down resistors (≈100kΩ) ensure the gates default to OFF if inputs float. External 10kΩ pull-down resistors, though optional, sharpen falling edges by reducing input capacitance interaction (≈5pF). Unmatched delay between HIN and LIN–even 20ns–can violate dead-time requirements, leading to shoot-through currents exceeding 10A.

SD (pin 4), when driven HIGH, forces both gates OFF within 100ns regardless of input states. Tie SD to COM via a 1kΩ resistor if unused, preventing unintended shutdown from EMI. A direct hardwire to COM risks latch-up if transients exceed ±500mV on the pin.

Power and Ground Considerations

VCC (pin 6) powers the low-side driver and internal logic at 10–20V. A 1µF bulk capacitor plus a 0.1µF ceramic capacitor must sit within 3mm of VCC and COM to handle peak currents during switching. VCC below 9.5V activates undervoltage lockout, halting both gate outputs until recovery. COM serves as the primary return path; any voltage drop exceeding 100mV between COM and the MOSFET source corrupts gate drive thresholds.

Isolate high-current paths from logic traces on the PCB. Route VS, VB, and HO traces at least 0.5mm wide for 5A capability, while HIN, LIN, and SD require only 0.2mm. Ground planes beneath the driver IC should be uninterrupted to minimize inductance, which otherwise amplifies ringing during transitions.

Thermal vias adjacent to the IC’s thermal pad (if present) should carry heat to an internal layer; 4–6 vias with 0.3mm diameter reduce thermal resistance by ≈30%. Junction temperature above 125°C triggers thermal shutdown, ceasing all outputs until cooling below 100°C.

Parasitic inductance in gate drive loops–even 5nH–creates overshoot exceeding 30V during turn-off. Snubber networks (e.g., 1Ω ≠ 1nF in series) across each MOSFET gate-source mitigate this, but add propagation delay (≈15ns). Calculate dead-time based on worst-case delay plus 1.5× the snubber time constant to prevent overlap.

Step-by-Step Wiring of Half-Bridge Drivers with Power Transistors for Precision Motor Operation

Connect the high-side transistor’s gate to the driver’s HO pin through a 10Ω series resistor, ensuring rapid turn-on while preventing oscillations. Place a 1N4148 clamping diode across the gate-source terminals to suppress voltage spikes exceeding 20V. The control signal’s logic ground must tie directly to the driver’s COM pin–avoid floating grounds by using a star-point connection at the power supply’s negative terminal to minimize noise-induced misfiring.

Route the low-side transistor’s switching node to the motor via a 12AWG wire with ferrite beads at both ends to curb high-frequency ringing; this is critical for 24V systems where slew rates exceed 5V/ns. Implement a 100nF bootstrap capacitor between VB and VS–select X7R dielectric for stable capacitance under temperature swings. For dynamic braking, wire a freewheeling diode (e.g., STTH200L06) antiparallel to the motor terminals, ensuring reverse recovery time under 50ns to prevent shoot-through during PWM transitions.

Power Sequencing and Fault Mitigation

Enable the driver’s shutdown pin (SD) through a 5V logic-level optocoupler (e.g., PC817) for galvanic isolation–this isolates control circuitry from voltage transients up to 3kVpk. Insert a 10μF bulk capacitor at the VCC input to stabilize supply during current surges; position it within 2cm of the driver’s pins to maintain 30–100ns specification, preventing cross-conduction in half-bridge configurations.

Bootstrap Capacitor Selection and Connection Techniques for Half-Bridge Driver Layouts

Select a bootstrap capacitor value between 0.1µF and 1µF for switching frequencies above 50kHz, ensuring it exceeds the gate charge requirement of the high-side MOSFET by at least 10x. For 20kHz–50kHz applications, increase to 2.2µF–4.7µF to maintain voltage stability during longer off-periods. Low-ESR ceramic capacitors (X7R/X5R dielectric) are mandatory; avoid electrolytic or film types due to slower response times.

Connect the bootstrap capacitor directly across the driver’s VB and VS pins with traces under 5mm in length to minimize parasitic inductance. Use a ground plane beneath these traces to reduce EMI coupling, especially in noisy environments. For layouts where space constraints prevent direct placement, a small-value decoupling capacitor (100nF) can be added locally to VB, but the primary bootstrap component must remain closest to the pins.

The table below outlines recommended capacitor values based on load conditions and switching frequency:

Switching Frequency	Gate Charge (nC)	Bootstrap Capacitor (µF)	Maximum Off-Time (µs)
20kHz	50	4.7	50
50kHz	30	2.2	20
100kHz	20	1.0	10
200kHz+	10	0.1	5

For isolated designs, ensure the bootstrap path does not cross primary-secondary boundaries. If galvanic isolation is required, use a dedicated isolated DC-DC converter instead of relying on the bootstrap method. Common-mode currents can corrupt the bootstrap voltage, leading to erratic high-side activation.

Implement a schottky diode in series with the bootstrap capacitor to prevent reverse current during dead-time or fault conditions. Select a diode with a forward voltage drop under 0.5V and a reverse recovery time below 50ns to avoid false triggering. For high-voltage applications (>100V), use a diode rated at least 1.5x the bus voltage to prevent avalanche breakdown.

In multi-phase configurations, each half-bridge stage requires its own dedicated bootstrap network. Sharing capacitors across phases introduces coupling, causing voltage imbalance and potential shoot-through. For interleaved topologies, stagger the bootstrap recharging periods by adjusting the PWM dead-time to prevent simultaneous current surges.

Test bootstrap voltage ripple under load conditions using an oscilloscope with a differential probe. Target ripple below 5% of the nominal VB-VS voltage to prevent gate voltage oscillations. If ripple exceeds this threshold, increase the capacitor value or improve the layout by widening power traces and reducing loop area.

For transient-heavy loads (e.g., motor drives), add a small bulk capacitor (10µF–47µF) in parallel with the bootstrap component to compensate for rapid current demands. This prevents voltage sag during startup or direction reversals, where the high-side MOSFET requires sustained gate drive.