ATX 500W Power Supply Circuit Diagram Full Schematic Guide

Select models like the FSP ATX-500PNR or Corsair CX500 (2021) as reference–these units balance efficiency and simplicity while meeting Intel ATX12V v2.52 standards. Primary side starts with a bridge rectifier (GBU606 or similar), converting AC to pulsating DC before filtering via high-capacity electrolytics (2x 470μF/400V). Add a NTC thermistor (e.g., SL22 5D-9) in series to limit inrush current during startup.

For switching, pair a LLC resonant controller (such as Infineon ICE2HS01G) with a half-bridge MOSFET configuration (IPP60R125C6 or STW45NM50). Include snubber circuits (RC networks: 10Ω + 0.1μF) across each MOSFET to suppress voltage spikes during transitions. The transformer core should use PC40 or PC44 ferrite material (EER35 or ETD39 form factor), wound with primary-secondary interleaving to minimize leakage inductance–aim for <5μH on the 12V rail.

Secondary regulation relies on synchronous rectifiers (IRFB4110 or STH110N10F7) for +12V, +5V, and +3.3V rails. Use Schottky diodes (SB560 or VS-40CPQ060) for auxiliary outputs (5VSB, -12V) to reduce forward voltage drop. Voltage feedback loops employ TL431 error amplifiers with optocouplers (PC817) for isolation–tune compensation networks (10kΩ + 1μF) for 5% ripple tolerance across all rails. Overcurrent protection integrates current-sense amplifiers (MAX4372) on each rail with threshold resistors sized for 1.2x nominal load.

Layout demands 4-layer PCB with dedicated ground planes for primary/secondary sides, separated by a 3mm creepage gap. Place bulk capacitors (Nichicon LG or Rubycon ZL series) within 20mm of the switching components to minimize trace inductance. Heat sinks for MOSFETs and diodes should use thermal interface pads (TIM) (e.g., Bergquist 570) with 7°C/W rating or better. Test prototypes with an electronic load (Maynuo M98) under step-response conditions to verify transient response–target <5% undershoot/overshoot during 50%–100% load transitions.

Key Circuit Components in High-Efficiency PSU Blueprints

Begin by identifying the primary switching regulator stage–typically a half-bridge or active-clamp forward topology–for 450–550W units. Locate the pair of N-channel MOSFETs (e.g., Infineon IPW60R041C6 or equivalent) on the high-voltage DC rail, driven by a dedicated PWM controller like the Champion CM6901 or ON Semiconductor NCP1397. Ensure the gate drivers (often isolated via transformers or optocouplers like PC817) deliver clean 12V–15V signals with sub-50ns rise times to prevent shoot-through. Snubber circuits (R=10Ω–100Ω, C=1nF–10nF) across each MOSFET drain-source will suppress voltage spikes exceeding 600V, critical for daughterboard longevity.

Examine the auxiliary winding feedback loop, where a TL431 shunt regulator (or equivalent) precisely maintains +5VSB at 5.0V ±2%, drawing power from a dedicated 12V standby transformer. The main +3.3V and +5V outputs should rely on synchronous buck converters (e.g., Richtek RT8204) with 15A–20A inductors (common core: Kool Mu 77083-A7, 33µH typical). Cross-reference inductor saturation current against the maximum load–exceeding 80% duty cycle risks core overheating. For transient response, place 1000µF low-ESR capacitors (Nichicon UHE or Panasonic FM) at each output node; omit this and ripple may exceed 120mVpp under 50% load steps.

Verify the PFC stage: a boost converter (e.g., STMicroelectronics L6562A) should interface with a 180µF–220µF/450V bulk capacitor (Rubycon YXF or similar) and a 400V/6A bridge rectifier (GBU6K). The inductor (e.g., TDK B82477G4, 500µH) must handle 1.2A RMS current without audible noise–sub-50kHz switching exacerbates this. EMI filtering requires a two-stage common-mode choke (1mH–3mH) plus Class Y capacitors (2.2nF/250VAC) across line and neutral; non-compliance risks failing FCC Part 15 or CISPR 32. Final checks: probe the PSAVE pin (if present) for over-temperature shutdown (>100°C) and confirm OVP thresholds (typically +12V at 13.8V ±0.5V) via a 10kΩ pull-up resistor to the controller’s UVLO pin.

Key Components of a 500W PSU Circuit Design

Prioritize selecting a PFC (Power Factor Correction) choke with a saturation current at least 30% higher than the expected peak load. For a 500W-rated unit, a 2.2mH inductor with a 10A rating (e.g., Coilcraft PCV-2-222-10L) ensures stable operation under transient loads. Avoid cheap ferrite cores prone to saturation–opt for powdered iron or sendust for reduced EMI and thermal stress.

Critical semiconductor choices dictate efficiency and longevity. Use bridgeless totem-pole PFC ICs like TI’s UCC28180 for active correction, paired with 600V SuperJunction MOSFETs (e.g., Infineon IPW60R041C6). For secondary rectification, synchronous Schottky pairs (e.g., Vishay VS-10CTQ150PbF) reduce conduction losses by 15-20% compared to standard diodes. Ensure gate drivers (e.g., onsemi NCP51511) have

Main transformer: Core material (e.g., ETD44 3C95) must handle 120kHz+ switching with <1% flux density margin. Windings–primary (2x 0.5mm Cu, bifilar) and secondaries (1mm Cu for +12V, 0.2mm for +5V/3.3V)–require <2% leakage inductance.
Snubber networks: RC dampening (e.g., 1kΩ/2W + 2.2nF/1.6kV) across MOSFET drains suppresses voltage spikes. For 12V rails, add a 10μF/50V MLCC post-LC filter to reduce ripple below 50mVpp.
Protection ICs: Prioritize latching OCP (e.g., STMicro’s L6562) over hiccup modes. OVP/UVP thresholds should trigger at ±7% of nominal (e.g., +12.84V/-11.16V for 12V) with <1ms response.

Thermal management begins with PCB layout. Dedicate 6oz copper pours for high-current traces, particularly the +12V rail (minimum 4mm width for 20A). Mount the PFC MOSFET and transformer within 20mm of heatsinks; use aluminum extrusions with >5W/K thermal resistance. Polyimide film capacitors on input (4x 220μF/450V) must have <3% ESR at 100kHz to prevent inrush current damage. For fan control, implement a dual-speed circuit (e.g., ON/OFF at 50°C, full RPM at 70°C) using a thermistor placed mid-PCB.

Step-by-Step Tracing of High-Voltage Input Section

Begin by locating the EMI filter circuit immediately after the AC inlet. Identify the common-mode choke coils (typically two toroidal cores wrapped in thick wire) and X/Y-class capacitors (marked with safety certifications like X2 or Y2). Verify the capacitors’ voltage ratings–minimum 275VAC for X-class and 250VAC for Y-class–to ensure compliance with transient surge standards. Trace the line from the choke to the bridge rectifier, noting the presence of a thermistor (NTC) between the filter and rectifier; its resistance should drop from ~10Ω at cold state to ~1Ω under load.

Examine the bridge rectifier’s configuration: four diodes (e.g., 1N5408 or equivalent) arranged in a full-wave setup. Measure DC output across the smoothing capacitors–expect ~325VDC for 230VAC input. If the circuit includes a PFC stage, the next component will be an inductor (often with a ferrite core) followed by a boost diode (e.g., STTH8S06D) and a high-voltage MOSFET (e.g., IPA60R160P7). Confirm the MOSFET’s gate driver signal (typically 12V–15V PWM) with an oscilloscope before proceeding.

Key Measurement Points

After EMI filter: Test AC voltage should match input (230V/115V ±10%).
Post-bridge rectifier: DC voltage should align with √2 × VAC (minus diode drops).
PFC output: ~380–400VDC for active PFC designs; ±5VDC tolerance.
Thermistor bypass relay: Should engage after 1–2s, reducing NTC resistance to near-zero.

Isolate faults by checking for bulged/leaking capacitors–ESR values must not exceed 0.5Ω for 220µF/450V units. Use a multimeter in diode mode to test bridge rectifier diodes; forward voltage drop should be ~0.5–0.7V. For PFC circuits, inspect the boost diode’s reverse recovery time (trr ≤ 35ns for high-efficiency designs). Replace any components with deviant readings, ensuring replacements match original specifications exactly (e.g., voltage/current ratings, package size). Document impedance readings across each stage to establish a baseline for future troubleshooting.

Schematic Breakdown of +12V, +5V, and +3.3V Rails

Start by tracing the +12V rail from the primary transformer’s secondary winding, typically wound with thicker gauge wire to handle currents exceeding 30A. The AC output passes through a full-bridge rectifier–two diodes for half-wave rectification waste energy–before smoothing via bulk capacitors rated for 470µF or higher at 25V minimum. Use ESR values below 0.05Ω to prevent ripple exceeding 120mV under full load. Post-filtering, the line feeds into a multi-phase buck converter if active regulation is employed, or a single shunt regulator for simpler designs. Verify the PWM controller’s switching frequency stays above 100kHz to reduce inductor size while maintaining efficiency above 85%.

+5V and +3.3V rails often share a common secondary winding, split via separate winding taps or center-tapped configurations. The +5V rail demands precise regulation; a dedicated linear regulator or buck converter ensures stability, though linear regulators drop efficiency below 70% at higher currents. Opt for synchronous rectification instead of Schottky diodes if currents exceed 15A, cutting forward voltage losses from 0.5V to 0.1V. For +3.3V, prioritize low-dropout regulators (LDOs) with dropout voltages under 1V when sourcing from +5V, avoiding excessive heat dissipation. Both rails require output capacitors with low ESR–ceramic types like X5R or X7R in 22µF–100µF range–to suppress transient responses during load steps.

Isolate feedback loops for each rail to prevent cross-regulation issues. Use optocouplers with CTR >100% for galvanic isolation in flyback topologies, ensuring PWM controllers like UC3843 or TL494 receive clean feedback signals. Sample the output voltage at the furthest point from the converter, not merely at the capacitor, to account for PCB trace resistance. Include a 5V standby rail sourced from an auxiliary winding, rectified and filtered independently, to supply control circuitry during soft-off states.

Snubber circuits across MOSFET drains and diode cathodes mitigate high-frequency ringing, typically configured with 100Ω–1kΩ resistors in series with 1nF–10nF capacitors. Place components as close as possible to semiconductor leads to reduce parasitic inductance. For +12V, add TVS diodes (e.g., SMBJ16A) across outputs to clamp voltage spikes from inductive loads like cooling fans or HDDs, preventing damage to motherboard circuits.

Monitor load regulation by simulating worst-case scenarios: disconnect all loads except the rail under test, then reconnect them simultaneously. +12V should sag less than 5% (600mV), while +5V and +3.3V must stay within ±5%. Use a scope with 10x probes to measure ripple at 20MHz bandwidth; high-frequency noise often hides below DC-coupled measurements. Implement pre-load resistors (1W 10Ω) on +5V and +3.3V rails if the circuit lacks minimum load requirements, preventing output voltage drift above nominal values.

Thermal management dictates component placement: position the primary MOSFETs and rectifiers near the edge of the PCB with vias to a heatsink pad. Thermal vias under large capacitors improve heat dissipation but keep them away from high-impedance feedback traces to avoid noise coupling. For +3.3V LDOs, mount them on a dedicated copper pour connected to a chassis ground plane to sink heat without introducing ground loops. Test thermal performance under 50°C ambient with a FLIR camera, ensuring junction temperatures stay below 120°C for MOSFETs and 110°C for diodes.

Grounding strategy separates high-current returns from signal grounds to prevent interference. Star-point grounding at the main capacitor bank connects +12V, +5V, and +3.3V returns individually before merging at a single point near the transformer’s core. Analog control grounds (feedback, PWM) must trace away from switching nodes, ideally on a separate layer shielded by a solid ground plane. Avoid daisy-chaining grounds; each sub-circuit’s return should branch directly to the star point to minimize loop areas.

Finalize protection features by integrating current-limiting on all rails: sense resistors (5mΩ–10mΩ) in series with +12V outputs feed into comparators (e.g., LM393) set to trip at 120% nominal current. Latch the fault signal to shut down the PWM controller until manual reset. Overvoltage protection (OVP) requires zener diodes (15V for +12V, 6.2V for +5V/3.3V) to trigger a crowbar SCR, shorting the rail to ground if voltages exceed safe limits. Test these circuits by injecting 110% nominal voltage and verifying sub-1ms response times to prevent downstream damage.