Half Bridge SMPS Circuit Design and Schematic Guide for Engineers

Implement a two-transistor push-pull topology for 50–200 W DC-DC conversion with 50–100 kHz switching frequency to minimize transformer size while maintaining ≤2% output ripple. Use N-channel MOSFETs (e.g., IRFP460) with 1.2 µs dead-time to prevent shoot-through–adjust via gate drivers with built-in delay (UCC27425 recommended). Primary inductance should be calculated as L_p = (V_in × D_max) / (2 × f_sw × ΔI_L), where ΔI_L is 20–30% of peak current for stability.

Select a center-tapped transformer core (e.g., ETD39) with B_max = 0.3 T to avoid saturation–calculate turns ratio as n = V_out / (V_in × D), rounding n_sec to the nearest integer to reduce voltage spikes. Snap-action diodes (e.g., MUR1560) on the secondary side must handle 2× V_out + 10% reverse voltage; derate by 30% for reliability. Add a snubber network (1 nF + 1 kΩ) across each switch to clamp ringing below V_in + 20 V, ensuring MOSFET safe operating area compliance.

For closed-loop control, use a current-mode PWM (e.g., UC3843) with 100 kHz bandwidth–compensate with a type-3 network (R_c = 5.1 kΩ, C_c1 = 4.7 nF, C_c2 = 1 nF) to achieve 50° phase margin at crossover. Input capacitance should be sized as C_in = (I_in × D) / (f_sw × ΔV_in), targeting ΔV_in ≤ 5% ripple. Verify layout: keep high-current paths (≤20 mm) wide and parallel, with a ground plane beneath the controller to minimize noise coupling.

Key Design Principles for Dual-Switch Power Converters

Select MOSFETs with a breakdown voltage at least 1.5 times the input voltage to prevent avalanche failures during transient spikes. For example, with a 380V DC bus, use 600V or 650V devices like IXYS IXFH40N60 or Infineon IPW60R041C6. Ensure gate drivers have adequate current capability–typically 1–2A–for fast switching to minimize dead-time losses.

Implement a dead-time control circuit using a dual comparator (e.g., LM393) to prevent shoot-through. Dead-time should be set between 100ns and 300ns, depending on switching speed and parasitic inductance. Use a small RC network (10Ω + 1nF) on each gate to dampen ringing without significantly increasing rise/fall times.

Opt for a ferrite core transformer (e.g., EE42/20) with a turns ratio appropriate for the output voltage. For a 12V output, a 15:1 ratio works well with a 380V input. Wind primary and secondary in a bifilar arrangement to reduce leakage inductance, which should not exceed 5% of magnetizing inductance. Use Litz wire for frequencies above 100kHz to mitigate skin effect.

Place snubber circuits (RCD clamp) across the primary switches to absorb energy from leakage inductance. Values should be calculated based on the transformer’s leakage inductance: start with 10Ω, 2.2nF, and 1N4007 diode, then adjust via oscilloscope measurements. Avoid overly large snubber capacitors, as they increase switching losses.

For feedback, use a TL431 shunt regulator with an optocoupler (e.g., PC817). The error amplifier bandwidth should target 1/10th of the switching frequency. Compensate with a type-II or type-III compensator: a 10kΩ resistor in series with a 1µF capacitor for the integrator, and a 1kΩ + 100nF network for the zero-pole pair.

Ground loops introduce noise into control circuits. Route the power ground and signal ground separately, connecting them only at a single star point near the input capacitor. Use a 10Ω resistor in series with the feedback optocoupler LED to suppress high-frequency noise without affecting regulation accuracy.

Test the converter under worst-case conditions: minimum input voltage, maximum load, and elevated temperatures. Measure efficiency–target 85–90% for 100W designs–and verify output ripple (

Key Components Required for Push-Pull Power Converter Design

Select a MOSFET with breakdown voltage ≥ 600V (e.g., STW45NM60 or IXTK60N60) and R_DS(on) ≤ 0.5Ω to minimize conduction losses. Pair with ultrafast recovery diodes (t_rr ≤ 35ns, e.g., MUR860) for the rectifier stage, ensuring efficient commutation at switching frequencies ≥ 100kHz. Use a transformer core with N87 or 3C90 ferrite material, sized for ≥ 2x calculated power to prevent saturation at full load (e.g., ETD39 for 250W applications).

Component	Critical Specification	Recommended Part
Primary-side switch	VDSS ≥ 600V, RDS(on) ≤ 0.5Ω	IPP60R099C6, SPW47N60C3
Gate driver IC	1A sink/source, UVLO ≥ 12V	IR2110, UCC21520
Controller PWM	Fixed freq. ≥ 200kHz, soft-start	UC3845, L6565
Output capacitors	Low ESR, ripple current ≥ 3Arms	Nichicon UHE, Panasonic FR
Input bulk cap	≥ 100μF/W for hold-up	Rubycon ZLH, Kemet ALS30

Implement a two-stage LC filter on the DC input (L > 1mH, C ≥ 220μF) to suppress conducted EMI below EN55022 Class B limits. Use X2-class safety capacitors (e.g., WIMA MKP-X2) across primary-secondary winding paths for enhanced noise immunity. For feedback optocouplers, choose CTR ≥ 150% (e.g., PC817, HCPL-3120) with ≥ 3500V_RMS isolation. Size heat sinks for θ_JA ≤ 15°C/W based on worst-case P_diss = (I_rms)² × R_DS(on).

Step-by-Step Wiring of High-Side and Low-Side MOSFETs

Begin by ensuring the gate resistors for both upper and lower transistors match their switching characteristics. For a 100 kHz switching frequency, values between 10 Ω and 50 Ω suit most mid-power applications. Higher resistances reduce gate ringing but increase switching losses–balance is critical.

Connect the bootstrap capacitor directly between the floating gate driver output and the source of the high-side FET. Use a 0.1 µF ceramic capacitor rated for at least 25 V. Position it no farther than 10 mm from the driver IC to minimize parasitic inductance. Larger capacitors increase hold-up time but slow down turn-on edges.

Route the gate traces symmetrically to avoid imbalanced switching. Keep trace lengths under 30 mm and maintain equal widths (0.5–1.0 mm) for both high-side and low-side paths. Copper thickness of 2 oz reduces voltage drop during fast transients–critical for preventing false triggering.

Isolate the power ground from the logic ground with a star-point configuration. Tie the high-current return path of the low-side FET directly to the bulk input capacitor, while the logic ground connects only to the driver IC. Avoid daisy-chaining grounds, as even 50 mV differences can desynchronize switching.

Driver Signal Integrity

Use a dedicated gate driver IC with built-in dead-time control. For IR2110 or similar, set dead time between 50 ns and 200 ns to prevent shoot-through. Shorter dead times risk cross-conduction, while longer intervals increase body diode conduction losses. Verify timing with an oscilloscope before applying full load.

Twist the gate drive wires if forced to use cables longer than 10 cm. Untwisted pairs pick up switching noise from nearby inductors, causing erratic behavior. Shielded cables (e.g., RG-174) work best for layouts exceeding PCB constraints, but add 10–20 pF of capacitance that may slow edges.

Add a 10–20 kΩ pull-down resistor on each gate to ensure FETs stay off during power-up. Without this, floating gates can partially conduct, dissipating excessive heat. For high-side FETs, use a resistor between the gate and the source (floating node); for low-side FETs, connect it to ground.

Validate the setup under 20% of full load before progressing. Check for overshoot above 20 V on gate waveforms–indicative of inadequate gate resistance or excessive trace inductance. Replace underdamped oscillations with a 1–5 Ω series resistor or a small ferrite bead (e.g., Murata BLM18PG) near the gate driver output.

Selecting and Connecting the Transformer for Optimal Voltage Conversion

Choose a ferrite core transformer with a saturation flux density of at least 0.3 T and a core loss below 100 mW/cm³ at your operating frequency (typically 50–200 kHz). For a 48V to 12V conversion, use an ETD39 or PQ32/30 core with a turns ratio of 4:1, ensuring primary inductance is 100–300 µH to minimize switching losses. Verify core material (e.g., 3C95) for low hysteresis and eddy current losses at your target frequency.

Wind the primary and secondary with litz wire (strands sized for skin effect, e.g., 0.1 mm diameter for 100 kHz) to reduce AC resistance. Maintain precise interleaving–place primary and secondary layers alternately with minimal air gaps–using 3+3 or 4+4 layer configurations for

Connect the transformer to the switching stage via a snubber network (RC series: 2.2 Ω + 1 nF) across each primary MOSFET to suppress voltage spikes (>2× Vin). Use a split secondary with a center tap for full-wave rectification, pairing each tap with a Schottky diode (e.g., STPS20L15G) for

PWM Signal Generation for Dual-Switch Power Converter Control

Use a dedicated PWM controller IC like the TL494 or UC3843 to generate complementary gate-drive signals with dead-time insertion. Configure the IC’s oscillator for a switching frequency between 50–200 kHz, balancing efficiency and component size. Set the dead-time at 100–300 ns to prevent cross-conduction while minimizing switching losses. Connect the controller’s output pins to two totem-pole drivers (e.g., IR2110) for reliable high-side and low-side MOSFET activation.

For adjustable duty cycle control, feed a closed-loop error amplifier output into the PWM comparator. Implement overcurrent protection by tying the shutdown pin to a current-sense resistor via a comparator (LM393). Ensure the feedback network uses an optocoupler (PC817) for galvanic isolation between primary and secondary sides, with a 1–10 kΩ series resistor to limit LED current. Compensate the loop with a Type 2 or Type 3 amplifier (e.g., TL431 + RC network) to stabilize transient response.

• Dead-time optimization: Start with 200 ns; reduce in 20 ns increments while monitoring MOSFET case temperature (<85°C).
• Driver stage: Use bootstrap capacitors (0.1–1 μF, X7R) for high-side drive, recharged via a diode (1N4148) during low-side conduction.
• Thermal considerations: Mount PWM IC on a 2 oz copper pour (~50 mm²) for passive cooling; derate switching frequency above 100 kHz by 20% if ambient exceeds 60°C.

Advanced Modulation Techniques

Implement phase-shifted PWM (PS-PWM) for reduced EMI by splitting the switching period into two staggered intervals. Use a CPLD or microcontroller (e.g., STM32F334) to generate four 90° phase-shifted signals with precise 1–2 μs overlap control. For resonant topologies, combine PWM with frequency modulation (FM) using a sawtooth oscillator (LM324) and voltage-controlled oscillator (CD4046). Limit maximum duty cycle to 85% to reserve headroom for transient events, using a Zener diode (5.1V) clamp on the feedback path.