Full Raspberry Pi 3 Model B+ Circuit Schematics and Board Layout Guide

For detailed hardware analysis, begin with the official Broadcom BCM2837B0 datasheet–specifically pages 12 through 28 covering power distribution, clock trees, and I/O mapping. This document omits generic block diagrams in favor of exact pin assignments and trace routing, which are critical for reverse-engineering or custom peripheral integration.

Obtain the verified KiCad project files from the Pi Forum Hardware Archive–look for the thread titled “BCM2837B0 Full PCB Trace Reconstruction.” These files include copper layers separated by voltage domains (1.8V, 3.3V, 5V), annotated test points, and decoupling capacitor placements. Avoid third-party “schematic snapshots” that often mislabel GPIO banks or omit USB PHY details.

Key subsystems requiring focus:

• Power Delivery: The AP2553W6-3.3TRG PMIC handles core, SDRAM, and peripheral rails. Probe resistors R1-R4 near the micro-USB input to confirm dropout behavior under 5A load.
• Ethernet PHY: The LAN7515 integrates RMII and USB hub functions. Trace differential pairs between the SoC and RJ45 jack–length matching errors on these lines cause >20% packet loss at 100Mbps.
• HDMI: The BCM VideoCore IV outputs via TMDS channels at 1.65Gbps. Verify pull-ups on CEC, DDC, and HPD lines–common failure points in DIY carrier boards.

For troubleshooting, use a thermal camera to identify hotspots beyond the expected AP2553W6 (Tj >85°C) or SoC (Tj >70°C). The LAN7515’s underside should never exceed 65°C under prolonged 94Mbps transfers. If temperatures rise higher, check decoupling capacitors C45-C52 near the PHY’s 3.3V rail for dielectric breakdown.

Technical Blueprints of the Pi 3 B+ Single-Board Computer

Download the official BCM2837B0 circuit reference from the manufacturer’s engineering portal before reverse-engineering power delivery subsystems. The 5V rail tolerances (+/- 5%) are documented on sheet 7, while sheet 12 details USB overcurrent thresholds (1.1A per port). Deviations beyond these specifications risk permanent PMIC failure.

Examine the AP2553 load switch configuration (U33) for precise downstream voltage regulation–schematics indicate a 1.2 MHz switching frequency with internal compensation. If modifying for dual-boot setups, solder a 10μF tantalum capacitor on the EN pin to suppress voltage spikes during boot transitions, especially when toggling between 3.3V and 1.8V IO domains.

Component	Designator	Sheet	Function
PMIC	U13 (MxL7704)	5	Multi-phase buck conversion (3.3V, 1.8V, 1.2V)
Ethernet PHY	U5 (LAN7515)	10	Gigabit MAC with integrated magnetics (10/100/1000)
Wi-Fi/BT module	U6 (CYW43455)	9	2.4/5 GHz 802.11ac + Bluetooth 4.2 LE

Trace the HDMI CEC line (pin 40 on the GPIO header) directly to the BCM2837B0 ball grid array–interference here disrupts remote wake functionality. Use shielded twisted pair (STP) for extensions exceeding 15cm, and terminate with a 120Ω resistor to prevent signal reflection. The schematic’s test points (TP2, TP3) confirm CEC line integrity with expected 0.4Vpp during active communication.

For custom carrier boards, replicate the LTC4412 ideal diode controller (U1) to manage USB VBUS sourcing/sinking. The reference design specifies an Rds(on) of 25mΩ at 25°C–substitute with lower-impedance FETs (e.g., NTJD4001N) only if thermal modeling validates junction temperatures below 100°C during sustained 2A loads.

Analyze the DS1339C+ RTC (U7) footprint on sheet 14 for battery-backed timekeeping–missing pull-up resistors (4.7kΩ) on SDA/SCL lines cause I²C bus lockups. Add these discretes if interfacing with I²C devices sharing the same bus, particularly depth sensors requiring

When probing the SDRAM lanes (LPDDR2-533), note the dedicated termination network (sheet 3) anchored by 24Ω series resistors and 47pF decoupling capacitors. Swapping these for high-speed oscilloscopes? Enable AC coupling and set probe attenuation to 10:1 to avoid falsely triggering on DDR calibration sequences (~500mV differential swings).

The LAN7515 Ethernet PHY’s power sequencing (sheet 10) mandates a 100ms delay between 3.3V_AVDD ramp-up and 1.2V_VDDC stabilization–violating this order suspends link negotiation. Implement this delay with a MIC2779L supervisory IC if designing auxiliary boards without PMIC coordination.

Critically, the CYW43455 Wi-Fi module’s SDIO interface (sheet 9) shares clock lanes with the eMMC controller. Avoid bit-banging SPI during wireless transmission; instead, multiplex GPIO 22–27 for auxiliary sensors only after loading the brcmfmac driver firmware, as undocumented driver conflicts corrupt ARP tables.

Official Sources for BCM2837B0-Based Board PCB Layouts

The primary repository for all single-board computing hardware documentation is GitHub, specifically the official hardware repository. This includes Gerber files, DXF outlines, and layered CAD data for the 3B+ variant, allowing direct fabrication or design adaptation. Navigate to the /hardware/computemodule/cmio/circuit_reference directory to locate board geometry, drill charts, and copper stackup details in industry-standard formats like Altium Designer Project (.PrjPcb) and ODB++.

For engineers requiring EDA-compatible design files, the Foundation provides KiCad schematics and PCB footprints via their datasheets portal. Download the PCB Mechanical Drawings PDF for exact board dimensions, fiducial locations, and component placement coordinates. Additional layers–silk screen, solder mask apertures, and paste stencils–are embedded in the same archive, ensuring compliance with automated assembly workflows.

Certified manufacturers should refer to the Compute Module IO Board Design Guide, which details trace impedance specifications, decoupling capacitor placement, and via stitching strategies for USB 2.0/Ethernet signal integrity. The guide also includes validated layout clips for the LAN7515 USB hub and BCM43455 wireless module, essential for replicating RF performance in derivative designs. Access requires registration at the official compute module documentation hub.

To procure bare PCB fabrication files without reverse-engineering, request the 3B+_Gerber.zip package from approved distributors like Newark or Digi-Key. These archives bundle Excellon drill tapes, IPC-356 netlists for flying probe testing, and solder paste definitions. Note that schema revisions (e.g., v1.3 vs. v1.4) introduce minor copper pad adjustments for improved DFM–verify the revision history in the readme.txt before committing to production.

For open-source EDA users, the GitHub PCB repository hosts fork-compatible projects in KiCad and Eagle formats. Clone the bcm2837-based branch to access annotated copper pours, controlled-depth vias for thermal relief, and ground plane segmentation rules. Contributors must adhere to the CERN-OHL-S licensing terms, permitting modifications but requiring attribution for derivative works.

High-reliability applications should cross-reference the Board Support Package (BSP) documentation with the PCB layout files. The BSP outlines critical trace constraints for the PMIC (MxL7704), DDR2 memory interface, and HDMI lanes–omitting these may lead to stability issues under load. These specifications are buried in the engineering blog archives, alongside thermal vias counts and heatsink footprint recommendations.

If undertaking reverse-engineering, prioritize X-ray or computed tomography scans to extract inner-layer routing, which the Foundation’s files omit. Tools like KS Circuits’ KiCad importer can convert Gerber stacks back into editable schematics, but expect discrepancies in via tenting and silkscreen. Validate extracted nets against the Broadcom BCM2837 datasheet to reconcile pinouts for GPIO, SPI, and clock domains.

For compliance testing, the CE/FCC certification reports include test coupon layouts mimicking the 3B+’s four-layer stackup (1/2 oz copper, 1.0 mm core). These coupons, hosted on the FCC ID database under ID 2ABCB-RPI3BP, reveal trace-width tolerances for 10/100 Ethernet and microSD interfaces, critical for passing conducted emissions tests. Save the TestSetup-PCB-RevX.pdf files to reference probe points during debug.

Key Components Highlighted in the Pi 3 B+ Block Diagram

Examine the central processing unit (CPU) allocation in the BCM2837B0 system-on-chip (SoC) first–its quad-core Cortex-A53 cluster runs at 1.4GHz, but thermal throttling begins at 60°C; preemptive cooling solutions (e.g., heatsinks or small fans) are mandatory for sustained loads above 70%. The Videocore-IV GPU operates at 400MHz, but its power remains untapped without firmware optimization; adjust config.txt parameters like gpu_freq and h264_freq to match hardware-accelerated workflows (e.g., 1080p60 decoding).

• Power delivery demands scrutiny: The AP2552 switch regulator feeds the SoC with 5V input, but peak current surges (≈2.5A) during CPU/GPU bursts can trigger undervoltage warnings–stabilize with a 2.5A+ PSU or dedicated buck converter.
• RAM allocation splits dynamically: The LPDDR2 (1GB) executes shared memory tasks; verify vcgencmd get_mem outputs to confirm GPU/CPU splits (default 64MB/remainder, adjustable via gpu_mem).
• Network interfaces reveal hidden constraints: The Gigabit Ethernet (via USB 2.0 bridge) peaks at 300Mbps real-world throughput, while the 802.11ac Wi-Fi (CYW43455) requires antenna tuning for consistent 5GHz performance–relocate interference sources or switch to 2.4GHz channels 6–11.

Peripheral connectivity hides critical voltage-level nuances: The HDMI output (TMDS at 1.8V) draws ≠1.2W under 4K30 loads–reduce resolution to 1080p60 if power budget is tight. USB ports (LAN9514 hub) share bandwidth; attach high-speed devices (e.g., SSDs) directly to the SoC’s USB 2.0 root to avoid bottlenecks. GPIO pins tolerate 3.3V logic only; exceeding this (e.g., via 5V Arduino shields) risks permanent damage to the BCM2837B0–use level shifters or opto-isolators for 5V compatibility. For unorthodox peripherals (e.g., LoRa modules), verify the PCM/I2S and PWM pin assignments in the block diagram to avoid conflicts with default kernel drivers.